Course Information
SemesterCourse Unit CodeCourse Unit TitleT+P+LCreditNumber of ECTS Credits
6EEM 308Digital System Design I3+0+035

Course Details
Language of Instruction Turkish
Level of Course Unit Bachelor's Degree
Department / Program Electrical and Electronics Engineering
Mode of Delivery Face to Face
Type of Course Unit Elective
Objectives of the Course Learning digital system design. To learn design processes with field programmable gate arrays.
Course Content FPGA and ASIC processes, Hardware description languages, VHDL and digital design principles, Combination circuit design with VHDL, Sequential circuit design with VHDL.
Course Methods and Techniques
Prerequisites and co-requisities None
Course Coordinator None
Name of Lecturers Asist Prof.Dr. Övünç POLAT
Assistants None
Work Placement(s) No

Recommended or Required Reading
Resources Sarıtaş, Engin ; Sedat Karataş, Her Yönüyle FPGA ve VHDL, Palme Yayıncılık, 2013.
Perry, Douglas L., VHDL : programming by example, McGraw-Hill, 2002.


Planned Learning Activities and Teaching Methods
Activities are given in detail in the section of "Assessment Methods and Criteria" and "Workload Calculation"

Assessment Methods and Criteria
In-Term Studies Quantity Percentage
Mid-terms 1 % 30
Quizzes 1 % 10
Final examination 1 % 60
Total
3
% 100

 
ECTS Allocated Based on Student Workload
Activities Quantity Duration Total Work Load
Course Duration 14 3 42
Hours for off-the-c.r.stud 14 2 28
Assignments 7 2 14
Mid-terms 1 12 12
Project 1 24 24
Final examination 1 24 24
Total Work Load   Number of ECTS Credits 5 144

Course Learning Outcomes: Upon the successful completion of this course, students will be able to:
NoLearning Outcomes
1 Learns the concepts of digital system design.
2 To be able to design and implement digital circuits under realistic constraints.


Weekly Detailed Course Contents
WeekTopicsStudy MaterialsMaterials
1 Introduction to Digital Systems Design
2 FPGA and ASIC processes
3 Hardware description languages
4 VHDL and digital design principles.
5 Combinational circuit design with VHDL
6 Combinational circuit design with VHDL
7 Combinational circuit design with VHDL
8 Midterm
9 Sequential circuit design with VHDL
10 Sequential circuit design with VHDL
11 Sequential circuit design with VHDL
12 Creation of testbench
13 Creation of testbench
14 Project presentations


Contribution of Learning Outcomes to Programme Outcomes
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11
All 4 5 5 5 4 3 1 3 3 3 3
C1
C2

bbb


https://obs.akdeniz.edu.tr/oibs/bologna/progCourseDetails.aspx?curCourse=2429220&lang=en