Course Information
SemesterCourse Unit CodeCourse Unit TitleT+P+LCreditNumber of ECTS CreditsLast Updated Date
7EEE 433Advanced Logic Circuit Design Lab.0+3+02424.08.2022
Course Details
Language of Instruction Turkish
Level of Course Unit Bachelor's Degree
Department / Program Electrical and Electronics Engineering
Type of Program Formal Education
Type of Course Unit Elective
Course Delivery Method Face To Face
Objectives of the Course The aim of the course is to present advanced logic design and implementation techniques that could be applied on Programmable Logic Devices (PLD) and Field Programmeble Gate Arrays (FPGA). Verilog Hardware desicription Language will be introduced and advanced logic simulation tehniques will be presented.
Course Content State reduction in fully specified sequential machines. Status coding in synchronous sequential circuits. Analysis of asynchronous sequential circuits. Design of asynchronous sequential circuits. State reduction in partially specified sequential machines. Status coding methods. Failure in asynchronous sequential circuits, iterative circuits, sequential arrays.
Course Methods and Techniques
Prerequisites and co-requisities None
Course Coordinator None
Name of Lecturers Associate Prof.Dr. Övünç POLAT
Assistants None
Work Placement(s) No

Recommended or Required Reading
Resources Dervişoğlu, A. (2002). İleri Lojik Devre Tasarımı Ders Notları. Alternatif Yayıncılık.
Floyd, T. L. (2009). Digital Fundamentals. 10/E, Prentice Hall.
Lala, P. K. (2007). Principles of Modern Digital Design. John Wiley&Sons Inc.

Course Category
Mathematics and Basic Sciences %20
Engineering %30
Engineering Design %30
Science %20

Planned Learning Activities and Teaching Methods
Activities are given in detail in the section of "Assessment Methods and Criteria" and "Workload Calculation"

Assessment Methods and Criteria
In-Term Studies Quantity Percentage
Mid-terms 1 % 30
Assignment 1 % 10
Final examination 1 % 60
Total
3
% 100

 
ECTS Allocated Based on Student Workload
Activities Quantity Duration Total Work Load
Hours for off-the-c.r.stud 8 3 24
Assignments 3 8 24
Presentation 3 8 24
Mid-terms 1 3 3
Laboratory 14 3 42
Final examination 1 3 3
Total Work Load   Number of ECTS Credits 4 120

 
Course Learning Outcomes: Upon the successful completion of this course, students will be able to:
NoLearning Outcomes
1 to be able to design synchronous and asynchronous digital circuits using Verilog hardware description language
2 to be able to simulate advanced digital circuit designs on state of the art FPGA simulators and draw conclusions from the results.
3 To be able to optimize and implement advanced digital circuit designs on PLD and FPGA devices using Electronic Design Automation(EDA) tools.
4 To be able to use Logic Analyzers to validate a logic design.

 
Weekly Detailed Course Contents
WeekTopicsStudy MaterialsMaterials
1 Introduction, Review of digital circuit design methods, Introduction to Verilog
2 Implementation technologies, Programmable Logic gates, Optimal implementation of numerical functions,
3 Verilog data types and operators, modular and gates, gate level modeling, time simulations Lab: Introduction of CPLD / FPGA Boards
4 Verilog behavior models, number representations, arithmetic circuits, Arithmetic operators, Lab: Determination of the project topic
5 Combinational circuit design with Verilog, Lab: Introduction to Digital Analyzer
6 Combinational logic circuit blocks, encoders / coders, arithmetic comparators etc.
7 Review
8 midterm
9 Basic Latching circuits with Verilog, master-slave and edge triggered flip flops, counters etc.
10 Synchronous digital circuits with Verilog, design process
11 Mealy & Moore machines, finite state machines, state reduction
12 Finite state design examples,
13 Micro-transaction based designs, hardware and software IP cores

 
Contribution of Learning Outcomes to Programme Outcomes
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11
All 5 5
C1
C2
C3
C4

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