Course Information
SemesterCourse Unit CodeCourse Unit TitleT+P+LCreditNumber of ECTS CreditsLast Updated Date
7EEE 421Integrated Circuits and Systems3+0+03524.08.2022
Course Details
Language of Instruction English
Level of Course Unit Bachelor's Degree
Department / Program Electrical and Electronics Engineering
Type of Program Formal Education
Type of Course Unit Elective
Course Delivery Method Face To Face
Objectives of the Course Knows the two-way communication between microcomputers when recognizing programmable elements.
Course Content VLSI design techniques and foundations. ASIC design, gate-arrays, standard-cells. Full custom design approaches. Floorplanning in chip-level. Separation of the system building blocks. Standard cell placement & routing algorithms. Verification of design, logic simulation, timing simulation, transistor level simulation. Design techniques for regular building blocks: memory arrays, PLAs. Testable system design techniques. Reliability. Introduction of improving VLSI design techniques and tools. Introducing of the CADENCE VLSI design environment. Examining the VLSI Design Flow. System level architectural design. Logic design and verification. Usage of VERILOG environment. Automatic synthesis of logic design. SYNOPSYS environment. Introduction of standard-cell libraries and their usage. Standard cell placement & routing. Full custom design strategies. Layout design in CADENCE - ARTIST design environment. Chip-level floorplanning and power distribution. VLSI test methods and design for testability.
Course Methods and Techniques
Prerequisites and co-requisities ( EEM 370 )
Course Coordinator None
Name of Lecturers Instructor Dr. Yalçın ALBAYRAK
Assistants None
Work Placement(s) No

Recommended or Required Reading
Resources Hideki İmai, Mobile Communication Sequrity, Artech House, October 2005.
Anand R. Prasad, 802.11 WLAN and IP Networking: Security, QoS and Mobility, Arteck House 2005. K.Daniel Wong, Wireless Internet Telecommunications, Artech House, October 2005.

Course Category
Engineering %40
Engineering Design %40
Field %20

Planned Learning Activities and Teaching Methods
Activities are given in detail in the section of "Assessment Methods and Criteria" and "Workload Calculation"

Assessment Methods and Criteria
In-Term Studies Quantity Percentage
Mid-terms 1 % 30
Assignment 2 % 20
Final examination 1 % 50
Total
4
% 100

 
ECTS Allocated Based on Student Workload
Activities Quantity Duration Total Work Load
Course Duration 14 3 42
Hours for off-the-c.r.stud 14 3 42
Assignments 2 9 18
Presentation 3 9 27
Mid-terms 1 3 3
Final examination 1 3 3
Total Work Load   Number of ECTS Credits 5 135

 
Course Learning Outcomes: Upon the successful completion of this course, students will be able to:
NoLearning Outcomes
1 Recognizes programmable interface chips
2 Can interconnect with the use of handshake signals and interrupt
3 designs bidirectional communication between two microcomputers
4 Knows direct memory access and DMA controllers

 
Weekly Detailed Course Contents
WeekTopicsStudy MaterialsMaterials
1 VLSI design techniques and foundations
2 ASIC design, gate-arrays, standard-cells
3 Full custom design approaches
4 Floorplanning in chip-level. Separation of the system building blocks
5 Standard cell placement & routing algorithms
6 Verification of design, logic simulation, timing simulation, transistor level simulation
7 Design techniques for regular building blocks: memory arrays, PLAs. Testable system design techniques,PLAs
8 Testable system design techniques. Reliability. Introduction of improving VLSI design techniques and tools
9 Introducing of the CADENCE VLSI design environment. Examining the VLSI Design Flow
10 System level architectural design. Logic design and verification. Usage of VERILOG environment
11 Synthesis of logic design. SYNOPSYS environment. Introduction of standard-cell libraries and their usage
12 Standard cell placement & routing. Full custom design strategies
13 Layout design in CADENCE - ARTIST design environment
14 Chip-level floorplanning and power distribution. VLSI test methods and design for testability.
 

 
Contribution of Learning Outcomes to Programme Outcomes
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11
All 5 5
C1 5 5
C2 5 5
C3 5 5
C4 5 5

  bbb